The present invention generally relates to response interval monitors and, more particularly, to devices for monitoring the occurrences of delayed responses and for discriminating against responses which are delayed in excess of a maximum allowable time.
When designing a logic network to control a sequence of events, a shift register can be used. At the start of the sequence, the register is initialized to all "0's" with the first stage being set to a "1". The register is clocked at a uniform rate and the position of the "1" bit within the register at any given time is used to initiate the particular event within the sequence of events which is desired to occur at the given time. The shift register technique provides many advantages, especially in large scale integrated circuit design. One of the more important advantages is that the shift register, when orthogonally clocked, provides complete control of the sequence at all times by eliminating race conditions.
If the sequence being controlled is of the demand-response type and a limit is placed on the allowable time to wait for a given response, then a uniformly clocked shift register implementation cannot be used. It becomes necessary that the shift register be provided, in effect, with a variable number of stages which can be dynamically altered in accordance with the interval taken by each timely response.